When the digital circuit outputs a high level, the current drawn from the power supply Ioh and the current Iol injected at the low level output are generally different, that is, Iol>Ioh. The TTL NAND gate in the following figure illustrates the formation of a spike current:
The output voltage is shown in the figure (a) on the right. Theoretically, the waveform of the power supply current is shown in the right figure (b), and the actual power supply current is as shown in the right figure (c). It can be seen from Figure (c) that the supply current has a short and large amplitude spike when the output transitions from low to high. The waveform of the peak supply current varies with the type of device used and the capacitive load connected to the output.
The main reasons for the spike current are:
The T3 and T4 tubes of the output stage are simultaneously turned on in the short design. During the NAND gate output low level to high level, the negative transition of the input voltage produces a large reverse drive current in the base loop of T2 and T3, because the saturation depth of T3 is designed to be better than T2. Large, reverse drive current will cause T2 to first de-saturation and turn off. After T2 is turned off, its collector potential rises, turning T4 on. However, at this time, T3 is not out of saturation, so in a very short design, T3 and T4 will be turned on at the same time, resulting in a large ic4, causing the supply current to form a peak current. R4 in the figure is designed to limit this spike current.
The R4 in the low-power TTL gate is large, so its peak current is small. When the input voltage changes from low level to high level, the NAND gate output level changes from high to low, and T3 and T4 may also be turned on at the same time. However, when T3 starts to conduct, T4 is in an amplified state, and the collector-injection voltage of the two tubes is large, so the peak current generated is small, and the influence on the power supply current is relatively small.
Another cause of spike currents is the effect of load capacitance. The NAND gate output actually has a load capacitance CL. When the output of the gate transitions from low to high, the supply voltage is charged to the capacitor CL by T4, thus forming a spike current.
When the output of the NAND gate transitions from a high level to a low level, the capacitor CL is discharged through T3. At this time, the discharge current does not pass through the power source, so the discharge current of CL has no effect on the power supply current.
Peak current suppression method:
1. Take measures on the circuit board wiring to minimize the stray capacitance of the signal line;
2. Another method is to try to reduce the internal resistance of the power supply so that the peak current does not cause excessive power supply voltage fluctuations;
3. The usual practice is to use a decoupling capacitor to filter, usually at the power inlet of the board.
A 1uF ~ 10uF decoupling capacitor filters out low frequency noise; a 0.01uF ~ 0.1uF decoupling capacitor (high frequency filter capacitor) is placed between the power supply and ground of each active device in the board. Filter out high frequency noise. The purpose of filtering is to filter out the AC interference superimposed on the power supply, but the larger the capacitor capacity is, the better, because the actual capacitance is not an ideal capacitor and does not have all the characteristics of an ideal capacitor.
The decoupling capacitor can be selected according to C=1/F, where F is the circuit frequency, that is, 0.1uF for 10MHz and 0.01uF for 100MHz. Generally take 0.1~0.01uF.
The high-frequency filter capacitor placed in the active device has two functions, one is to filter out high-frequency interference conducted along the power supply, and the other is to timely supplement the peak current required for high-speed operation of the device. Therefore, the placement of the capacitor is something to consider.
The actual capacitance is equivalent to the resistance and inductance connected in series to the capacitor due to parasitic parameters, which is called equivalent series resistance (ESR) and equivalent series inductance (ESL). Thus, the actual capacitance is a series resonant circuit whose resonant frequency is:
The actual capacitance is capacitive at frequencies below Fr and inductive at frequencies above Fr, so the capacitance is more like a band-stop filter.
The 10uF electrolytic capacitor has a large ESL and Fr is less than 1MHz. It has a good filtering effect for low-frequency noise such as 50Hz, and has no effect on high-frequency switching noise of hundreds of megabytes.
The ESR and ESL of a capacitor are determined by the structure of the capacitor and the medium used, not the capacitance. By using a larger capacity capacitor, the ability to suppress high-frequency interference is not improved. For the same type of capacitor, at a frequency lower than Fr, the large-capacity is smaller than the small-capacity impedance, but if the frequency is higher than Fr, ESL determines There is no difference in the impedance between the two.
Excessive bulk capacitors on the board do not help to filter out high frequency interference, especially when powered by a high frequency switching power supply. Another problem is that there are too many large-capacity capacitors, which increases the impact on the power supply when the power is turned on and the board is hot-swapped. It is easy to cause problems such as a drop in the power supply voltage, a fire in the board connector, and a slow rise in the voltage inside the board.
Decoupling capacitor placement during PCB layout
For the installation of capacitors, the first thing to mention is the installation distance. The capacitor with the smallest capacitance has the highest resonant frequency and the smallest decoupling radius, so it is placed closest to the chip. A slightly larger value can be a little farther away, and the outermost layer has the largest value. However, all capacitors that are decoupled from the chip are as close as possible to the chip.
Figure 1 below is an example of a placement position. The capacitance level in this example generally follows a 10-fold hierarchical relationship.
It is also important to note that when placed, it is best to distribute it evenly around the chip, for each level of capacitance. Usually, the chip is designed to take into account the arrangement of the power supply and ground pins, which are generally evenly distributed on the four sides of the chip. Therefore, voltage disturbances exist around the chip, and decoupling must also be uniformly decoupled from the area where the entire chip is located. If the 680pF capacitor in the above figure is placed on the top of the chip, due to the decoupling radius problem, the voltage disturbance at the lower part of the chip cannot be well decoupled.
Capacitor installation
When installing the capacitor, pull a small lead wire from the pad and connect it through the via hole and the power plane. The ground terminal is the same. The current loop through the capacitor is: power plane -> via -> lead -> pad -> capacitor -> pad -> lead -> via -> ground plane, Figure 2 shows the current intuitively The return path.
The first method draws a very long lead from the pad and then connects the via, which introduces a large parasitic inductance and must be avoided. This is the worst way to install.
The second method punctured the pad at both ends of the pad, which is much smaller than the first method and has a small parasitic inductance that is acceptable.
The third type of hole punching on the side of the pad further reduces the loop area, and the parasitic inductance is smaller than the second one, which is a better method.
The fourth type is perforated on both sides of the pad. Compared with the third method, each end of the capacitor is connected to the power plane and the ground plane through the parallel connection of the via holes, which is smaller than the third parasitic inductance. Space allows, try to use this method.
The last method is to directly punch holes in the pad, and the parasitic inductance is the smallest, but the soldering may be problematic, depending on the processing capability and method.
The third and fourth methods are recommended.
One thing to emphasize is that some engineers sometimes use a common via for multiple capacitors in order to save space, and do not do this under any circumstances. It is best to find ways to optimize the design of the capacitor combination and reduce the number of capacitors.
The wider the trace, the smaller the inductance, and the lead from the pad to the via is as wide as possible, if possible, as much as the pad width. So even with the 0402 package capacitor, you can use a 20mil wide lead. The lead wire and via mounting are shown in Figure 4, paying attention to the various dimensions in the figure.
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