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With manual band selection, the lock time can be reduced from a typical value of 4.5 ms to a typical value of 360 μs.
This article uses the highly integrated demodulator and frequency synthesizer ADRF6820 as an example to show how to manually select the frequency band to shorten the PLL lock time.
The PLL lock process includes two steps:
1, automatically select the frequency band (coarse adjustment) through the internal loop. During register configuration, the PLL first switches and configures according to the internal loop. The PLL is then driven by an algorithm to find the correct VCO frequency band.
2, fine tune through the outer loop. The PLL switches to the outer loop. The phase detector and charge pump work in conjunction with the external loop filter to form a closed loop, ensuring that the PLL locks to the desired frequency. Calibration requires approximately 94,208 phase-detection phase detector (PFD) cycles; for a 30.72 MHz fPFD, this corresponds to 3.07 ms.
After the calibration according to the above steps, the feedback operation of the PLL locks the VCO to the correct frequency. The locking speed depends on the nonlinear cycle behavior. The PLL total lock time consists of two parts: VCO band calibration time and PLL cycle time. The VCO band calibration time only depends on the PFD frequency; the higher the PFD frequency, the shorter the locking time. The PLL cycle time is determined by the loop bandwidth achieved. When the loop bandwidth is narrower than the PFD frequency, a fractional-N/Integer-N synthesizer will have a cycle slip. The phase error at the PFD input accumulates too quickly and the PLL has no time to correct it. The charge pump temporarily draws charge in the wrong direction, which drastically shortens the lock time. If the ratio of the PFD frequency to the loop bandwidth is increased, the cycle slip will increase; for a given PFD cycle, increasing the loop bandwidth will shorten the cycle time.
Therefore, when using auto-calibration mode, the total lock time may be too long for some applications. This article proposes a scheme that significantly shortens the locking time by manually selecting the frequency band. The steps are as follows:
1
Power up the device according to the register initialization sequence shown in Table 1. By default, the chip operates in automatic band calibration mode. Register 0x02, Register 0x03, and Register 0x04 are set according to the desired LO frequency.
Table 1. Register initialization sequence
2
Read lock detection (LD) status bit. If LD is 1, it indicates that the VCO is locked.
3
Bits[5:0] of Register 0x46 are read back through the Serial Peripheral Interface (SPI). Assuming the value is A, the register values ​​corresponding to all required LO frequencies in the system are saved to EEPROM. This allows you to determine the table of frequencies and associated register values ​​(see Table 2).
Table 2. Lookup table
4
To shorten the LD time, place the ADRF6820 in manual band selection mode and program it manually using the data collected in step 3. The manual programming steps are as follows:
a. Set Register 0x44 to 0x0001: disable the band selection algorithm;
b. Set bit 7 of Register 0x45 to 1 to set the VCO band source to the saved band information instead of the band calculation algorithm. Bits [6:0] in Register 0x45 are set using the register value recorded in step 3;
c. Select the appropriate VCO frequency range through Bits[2:0] of Register 0x22 (see Table 3);
Table 3. VCO frequency range
d. Update Register 0x02, Register 0x03, and Register 0x04 according to the desired frequency. Register 0x02 sets divider INT value, ie VCO frequency / integer part of PFD; Register 0x03 sets divider FRAC value, (VCO frequency/PFD − INT) × MOD; Register 0x04 sets divider MOD value, ie PFD / Frequency resolution;
e. Monitor the LD to check if the frequency is locked. For example, PFD = 30.72 MHz and LO = 1600 MHz.
Table 4. Manual Band Calibration Register Sequence
Figures 1 and 2 show the lock detection time in the automatic band calibration mode and the manual band calibration mode, respectively. In Figure 2, a high on line 1 (lock detection) indicates that the PLL is locked. Line 2 (LE) represents the LE pin and is a trigger signal. Note: The lock detection time must be read from low to high.
Figure 1. Lockdown time in automatic band calibration mode, tested with a signal source analyzer
Figure 2. Lockdown time in manual band calibration mode with oscilloscope test
In automatic band calibration mode, the locking time is approximately 4.5 ms; in manual band calibration mode, the locking time is approximately 360 μs. The data was measured with 20 kHz loop filter bandwidth and 250 μA charge pump current configuration.
After verification, we can see that with manual band selection, the locking time has shortened from a typical value of 4.5 ms to a typical value of 360 μs. However, for each frequency, it is recommended to first determine the optimum band value using automatic band selection and save it, because the optimum band value varies from device to device, so this procedure must be performed for each ADRF6820. The VCO band does not need to be updated due to temperature changes.
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