An 8-bit or 16-bit CPU may be able to meet your current application needs. But in order to remain competitive, you must make continuous improvements to your product, including the need to continuously increase its new features, continually increase its speed, and reduce costs while increasing its specifications. If you don't do this and your competitors are doing it, you will be left open.
One way to maintain a competitive advantage is by gradually improving your existing design. But over time, the limitations of the architecture may be that the process is getting slower and more expensive. So you can port your design to 32 for the platform, which will improve the performance of your product in the following aspects.
Table 1: Advantages of porting to a 32-bit platform
Do you really need to port your product to a 32-bit platform?When you port a product that is an 8-bit CPU to a 32-bit CPU, there are a few things to consider. The first is whether your existing CPU is still available, and whether you can move the product to 32 for the platform can have an advantage or performance improvement. 8-bit applications typically implement basic perceptual and control through simple calculations. The 8-bit CPU performs well for bit operations and applications when the calculated value is below 256, such as a well-known architecture 8051.
Even the smallest 32-bit CPU can do everything an 8-bit CPU can do, as shown in Figure 1.
1. Ability to handle more complex calculations. For example, it includes the DSP, image processing, and gesture recognition functions that are included with the unit.
2. Data mining and analysis, database search.
3. Real-time multitasking system.
Figure 1 - Performance comparison of single-chip microcomputers using Dhrystone
Even if you don't need to use these powerful features, the 32-bit CPU can improve your design from the following aspects:
Power consumption: For example, a common low-power design: the CPU is in a low-power mode of sleep, wake up periodically and execute code in active mode (Figure 2). In both modes, a 32-bit CPU may require more power than an 8-bit CPU, but a 32-bit CPU takes less time to execute code. Therefore, 32-bit CPUs are more in low-power mode. In many cases, this may result in its average power being smaller than an 8-bit CPU.
Figure 2: Comparison of average energy consumption for computationally intensive tasks
Scalable: Now, most CPU sales are sold along with a product line that can be upgraded from low performance to high performance. If your product wants to be upgraded, then your CPU must also be upgradeable. CPU upgrades are from the following aspects:
1. The high-end members of the instruction set and series should have more instructions or more operating modes of existing instructions while maintaining backward compatibility with low-end members.
2. More registers, or existing registers, have more defined bits.
3. More functions, such as interrupt control and debugging.
The ARM Cortex-M processor family is the best example of a CPU scalable. As shown in Figure 3:
Figure 3 - Overview of the ARM Cortex-M Processor Family
Cost: There may be a perceived error that would take 32-bit CPUs to cost more. But with the development of technology, 32-bit CPUs are not necessarily more expensive than 8-bit CPUs, and now there are many low-cost 32-bit CPUs. For example, it is more cost-effective because of its simple design and the ARM Cortex-M0 core that occupies a small silicon area. For example, the Cypress Semiconductor entry-level PSOC 4000 CPU is only $0.29.
In addition, Table 1 shows that 32-bit CPUs that support high code density and faster execution speed can help reduce costs.
This is not just about the CPU.Usually only focus on porting your firmware code to a new CPU. However, keep in mind that the CPU is only part of the MCU, and the MCU can provide as much improvement as possible to its CPU to meet customer improvement requirements. E.g:
1. Can the peripherals of the MCU improve the functionality of the product?
2. Can peripheral devices operate with less code? Can you reduce the load on the CPU? This may result in the system using less memory and possibly reducing costs.
3. Can the device save you board and system level costs? For example, you can move certain functions on the PCB to the MCU.
4. Is the MCU flexible enough to adapt to changing needs without having to create a new board?
Finally, please note that microcontroller devices are usually supported only by the Integrated Development Environment (IDE). Make sure the new IDE is more than just an editor, compiler, and debugger. The IDE enables you to quickly build the entire application, use the hardware features of the microcontroller, and firmware to significantly speed up the design. Development kits and application notes are also helpful.
Code porting skillsIf you decide to port a design to a 32-bit CPU, keep these considerations in mind:
Choose an entry-level 32-bit CPU/microcontroller and IDE. As your first port to 32-bit device code, keep it simple, which will reduce the risk of introducing defects, and you will be familiar with the differences in 32-bit designs. Choosing a basic entry-level device and an IDE simplifies the migration process. An example of a Cypass semiconductor is the PSoC 4000 MCU, which is supported by the PSoC IDE.
Choose a new compiler. When you port your code to a new CPU, you must also choose a new compiler. A large number of compilers, some of which are free, are available for 32-bit CPUs. For example: GCC, ARM/Keil MD, IAR.
Let your build and debug tools work. Create a small test program, such as a flashing LED light. You will gain experience with new tools that will help you complete the steps below.
Assembly code rewriting. Ideally, your existing code should use C (or some other more advanced language). The assembly language code for any 8-bit processor is not portable. If you have any assembly code in your current design, consider rewriting it under C before you start the migration process.
Package special code. If your code is already modular (coding best practices). The porting of the code corresponds directly to the MCU registers, such as reading the I/O port, which should be separate from the rest of the file. Encapsulate the code in these files and name it by function, such as UART_Receive(). Then you can override these features for the new microcontroller without changing the rest of the code.
Other architecture changes to a new microcontroller may allow you to offload functions from the CPU to the peripherals. In addition, a new IDE can generate code automatically. With these features, consider rebuilding some or all of the code.
Because 32-bit CPUs are easier to implement task switching, consider re-constructing code as a separate set of tasks to be used by a real-time operating system (RTOS). For example: 32-bit system RTOS vendors Segger and Micrium.
Increased build and debug, the best way to design new code is to add, test, and debug code for a small portion of the code.
. This makes it easier to find and fix defects. The same applies to porting - porting, testing, and debugging code on new MCUs is also part of the process.
CPU and MCU examples, in order to better understand the migration process, let's take a closer look at the context of the ARM Cortex-M0 and PSoC 4000. The ARM Cortex-M0 processor is the smallest ARM core. Its register architecture (Figure 4) and instruction set make it support C tools.
Figure 4: Cortex-M0 Register Architecture
All registers are 32-bit, using 32-bit addressing and have a 4Gbyte address space. Most 8-bit CPUs are limited to 64Kbytes of address space.
There are 12 general purpose registers. (Low registers R0-R7 have more supported instruction sets). Special registers include:
Dual stack pointer (R13) to help implement a real-time operating system (RTOS)
The link register (R14) is quickly returned from the function call
Program counter (R15)
The Program Status Register (PSR) contains the result of the instruction such as the zero and hold flags and the current number of exceptions.
Interrupt mask register
Control register controls which stack pointer is valid
The Cortex-M0 core instruction set is simple but powerful and has a large number of processing modes. It has excellent code density. Porting C code from an 8-bit CPU to the Cortex-M, the CPU often uses less memory.
ARM Cortex-M series CPU instruction pipeline, as shown in Figure 5. This increases overall code execution speed because the CPU can fetch and decode subsequent instructions while executing an instruction.
Figure 5: Pipeline division in the Cortex-M processor
The ARM Cortex-M CPU family integrates support for interrupts directly into the CPU core, using a Nested Vectored Interrupt Controller (NVIC). NVIC features include:
Automatic dynamic priority and priority wait interrupt nestingLow latency - CPU automatically stores and restores its state without instructions overhead
Late - A high priority interrupt is executed first when a low priority interrupt service stack push operation arrives.
These features are faster and determine interrupt handling. The system timer "SysTIck" facilitates the use of the RTOS and can be operated on the CPU sleep, also included. There are high levels of interrupt support available, and you can consider changing your architecture to rely more on interrupt handling.
ARM's Cortex-M processor family integrates debugging functions in the CPU core, supporting multiple IDEs for easy debugging.
The Cortex-M0 core is part of the Cortex-M processor family, which has the same register architecture and executes some or all of the Thumb-2 instruction set, making it easier to upgrade to a more powerful CPU. For example, Cypress's PSoC 5 LP Cortex-M3 processor.
The PSoC 4000 is part of the entry-level PSoC 4 family. In addition to the Cortex-M0 processor, it has a flexible set of peripherals that can be dynamically configured, as shown in Figure 6.
Figure 6: PSoC 4000 Block Diagram
This type of CPU also has capacitive touch sensing characteristics. Capacitive sensing offers significant advantages over mechanical buttons in terms of cost, performance and anti-static protection.
Capacitive sensing features include:
Easy to implement buttons, scroll bars and proximity alarm solutions with 16 input paths per I/O pin
High signal-to-noise ratio (SNR) ensures touch accuracy in noisy environments
SmartSense automatically adjusts speed and does not require calibrationThe capacitive sensing block consists of two DACs and a comparator that you can use for other purposes if CapSense is not needed.
Cypress also offers PSoC development tools, an integrated design environment (IDE) for PSoC3, 4 and 5 LP devices. PSoC Development Tools is a free Windows-based IDE that supports PSoC-based system hardware and firmware design.
You can use classic, familiar schematics to design. Components include automatic generation of API code that can greatly reduce the amount of code you write. Using PSoC development tools is easy to implement design migration between PSoC series. As shown in Figure 7.
You can also export PSoC designs to other IDEs such as μVision and IAR.
Figure 7: PSoC development tools for component configuration
It is now simple to upgrade legacy 8 and 16 bit designs to 32-bit platforms while still meeting cost targets. Several factors must be kept in mind when planning to migrate to a new CPU; a primary 32-bit microcontroller to choose from and good IDE support.
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