A multi-function electronic code lock is implemented on the programmable logic device CPLD by using EDA technology. In order to make up for the deficiency of the traditional password lock and further improve the reliability, all the data storage and calculation in the system are completely realized by hardware. The behavior of the circuit is described using the VHDL language, and the EDA tool in the Quartus II software is simulated and downloaded. The entire design process uses a top-down approach with high design efficiency and low development costs. The MAXII series CPLD is adopted as the hardware core, and its power consumption is low, and the logic execution speed is much higher than that of the single-chip microcomputer. It has strong market competitiveness in the security industry.
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Traditional mechanical locks have poor anti-theft functions and cannot function in modern high-tech security systems. They have gradually been replaced by more reliable and intelligent electronic digital locks. At present, most of the password lock products on the market are based on single-chip microcomputers, which are controlled by software. In practical applications, the system stability is poor and the cost is high. This paper studies a pure hardware implementation of electronic code lock. To compensate for the shortcomings of traditional technology, EDA technology is used to implement password storage and operation on the programmable chip, so that the product has both hardware security and high speed. It also has the flexibility and ease of maintenance of software development.
1 Main technology and development environment
1.1 EDA technology and features
EDA (Electro nic Design Automation), the "electronic design automation", is currently the mainstream technology in the field of electronic design. EDA technology relies on a powerful electronic computer to automatically complete logic compilation, simplification, segmentation, synthesis, optimization and simulation on the EDA tool software platform for design files completed by hardware description language as system logic description. Download to a programmable logic device CPLD/FPGA or ASIC ASIC chip to implement specific electronic circuit design functions. Compared with traditional electronic design methods, EDA technology has the following main advantages:
(1) Computer simulation verification can be performed at various stages and levels of electronic design;
(2) Unique top-down electronic design;
(3) Make the designer have complete autonomy.
1.2 Hardware Description Language
VHDL (Very High Speed ​​Integration Circuits Hard-ware Des cription Language), which is the "super high-speed integrated circuit hardware description language", is the mainstream hardware description language in the field of electronic design.
It has good circuit behavior description capability and system description capability, and has features independent of the specific hardware circuit and independent of the design platform, so that the designer can concentrate on the realization of the system function without affecting the function. Process-related factors take too much time and effort.
1.3 Development environment
1.3.1 Software Platform
Quartus II is a new generation of development software from Altera that supports a variety of editing input methods, including graphics input methods, text-editing input methods based on hardware description languages, and memory editing input methods. It supports Al-tera's IP core and includes the LPM/MegaFunction megafunction library, allowing users to take advantage of proven modules to simplify their designs and increase development productivity.
As a programmable logic design environment, Quartus II has become the development tool of choice for designers. The design uses Quartus II version 9.0 as the development platform.
1.3.2 Hardware Platform
CPLD (Complex Programmable Logic Device) is a complex programmable device. Due to its flexible programming, high integration, short design and development cycle, low manufacturing cost and strong confidentiality, the hardware test of this paper is based on the MAXII series CPLD. Completed, the chip model is EPM240T100C5.
2 password lock function requirements
Currently, electronic password locks on the market only allow users to enter a fixed number of passwords. However, in practical applications, the number of passwords is too large, which is not convenient for the elderly users to remember, and the number of bits is too small, and it cannot meet some young users who have high requirements for safety performance. In this paper, based on the high integration and low cost of CPLD, the above shortcomings are overcome, and the user can set the number of passwords by himself. This function has certain advantages in the competition of products in the same industry.
The designed electronic password lock can do the following functions:
(1) Set the number of passwords of the password lock n;
(2) Input and display of n-digit password;
(3) verification of the password;
(4) alarm function;
(5) Clearing and modifying the password.
It mainly consists of a password input circuit, a core control circuit and a display output circuit. The input circuit comprises a matrix keyboard, a keyboard scanning circuit, a debounce circuit, a decoding circuit, etc.; the control circuit mainly performs the functions of inputting, checking, clearing and modifying the password; and the output circuit controls the display of the password value on the digital display.
3 hardware circuit design
3.1 Input circuit
This design uses a 4 × 3 matrix keyboard, as shown in Figure 1, it is composed of 4 I / O lines as row lines, 3 I / O lines as column lines, at each intersection of the row and line All set a button, there are a total of 12 buttons, respectively representing the number 0~9, the confirmation button and the setting button, as shown in Figure 1. If the user needs to set the number of passwords, you can press and hold the setting button for 3 s. After hearing the prompt tone, enter the password digits (this design only supports 4, 6, 8 digits for the time being); if you need to set a new password, you can short press Set the key, and then enter the new password after the prompt tone. The input circuit should have the functions of matrix keyboard scanning function, keyboard debounce function and decoding. Among them, the keyboard scanning adopts the line scanning mode, and the four I/O lines KEYR3~KEYR0 are the line scanning signals, wherein KEYR3 corresponds to the first line, KEYR2 corresponds to the second line, and so on.
Obviously, the order of change of the scanning signal is: 0111, 1011, 1101, 1110, and it is repeated. During the scanning process, when a key is pressed, the corresponding column signal read from KEYC2~KEYC0 is “0â€, and then the 4-bit row signal and 3-bit column signal value at this time are sent to the keyboard for decoding. The circuit decodes to get the exact key value. Conversely, if the values ​​read from KEYC2~KEYC0 are all "1", it means that no key is pressed, that is, no operation is performed. As shown in Table 1.
During the keyboard scan, the scan signal is constantly changing to determine the button press and lift. Fast-changing scan signals not only increase system power consumption, but also cause interference to other sensitive circuits [6-7]. Therefore, the following improvements must be made: change the scan mode to key-press trigger scan mode, that is, when a key After being pressed, the keyboard scanning circuit is triggered to generate the scanning timing. After the key is released, the scanning of the keyboard is stopped, so that the circuit is in a relatively static state to reduce the interference signal.
In addition, a small delay is added between the button press time and the start scan time, and the circuit is allowed to start scanning after the delay is over, which can avoid the erroneous input caused by the keyboard shake to the utmost.
The main VHDL code is described as follows:
3.2 Control circuit
The control circuit is the core circuit of the whole system, and the sub-circuit can be selected according to the number of passwords input by the user. Since the system allows the user to enter a 4-digit, 6-bit or 8-bit password, there are three sub-circuits, and the three-choice selector determines which of these circuits serves the user, as shown in Figure 2.
In Figure 2, en is the working enable of the three-select selector, which is initiated by the active reset signal of the input circuit. When the user presses the reset button on the matrix keyboard for 3 s, the input circuit will generate the en signal as '1', which will cause the selector Mux31 to start working. If the user wants to set the 6-digit password, then after the prompt tone Press the "6" button on the keyboard, the button signal will be transmitted to X6, and the selector determines that the subsequent control circuit is kong6.
The main VHDL code is described as follows:
For the subsequent control circuits kong4~kong8, there should be functions such as password clearing, storage, verification and modification. Since the number of operands is different, the VHDL language description process of these three circuits is almost repeated for the designer, thus greatly shortening the design cycle.
The storage of the password in the control circuit is implemented using registers.
The register is a typical sequential logic circuit. Under the control of a specific clock signal, a set of binary data can be loaded and stored stably. After the control signal is cancelled, the information is still stored in the register. Making full use of the incomplete if statement in VHDL can produce the characteristics of the sequential circuit, perform circuit description, and do not involve internal triggers, and the development efficiency is high.
3.3 output circuit
The output circuit accurately displays the result in decimal form on the output LED, and the password value on all LEDs is shifted to the left by one each time the user enters a password. This circuit is a purely combinatorial logic circuit that can be used to describe its circuit functions using case statements in the VHDL language.
Some VHDL codes are as follows:
Where: movesgl represents the left shift displacement; zin is the input signal; when movesgl is "000", it means no left shift; when it is "001", it means it needs to move once; "010" means it needs to move twice, This type of push. When the user enters a 6-digit password through the matrix keyboard, it needs to move 6 times to the left to achieve the dynamic left shift of the password on the LED digital tube.
4 Simulation and download
4.1 Simulation
Before the programming download, the EDA tool must be used to simulate the design results, ie simulation. Simulation is an important step in the EDA design process. The timing simulation used in this paper is the simulation closest to the operating characteristics of real devices, and the simulation accuracy is high. Taking a 4-digit crypto circuit as an example, a system simulation diagram is made, as shown in Figure 3.
As can be seen from Figure 3, through the input terminal zin, the password value "5623" is input successively, and the values ​​stored in s0, s1, s2, and s3 are updated in real time, and the waveform is analyzed, and the system basically meets the expected functional requirements. The output waveform is normal.
4.2 Download
In the Quartus II 9.0 software, the download steps using the integrated EDA tool are as follows:
(1) According to the pin characteristics of the programmable CPLD chip EPM240T100C5 in the development board, the ports of the top design entity of the system are pin-distributed.
(2) After the adapter is adapted, a download file in POF format is generated, and then the CPLD chip is programmed through the JTAG programming cable.
(3) Click the download button Start to download the target device. When the process progress shows 100%, the download is successful.
(4) The hardware was tested using the peripheral interface circuit on the development board. And use the embedded logic analyzer SignalTap II to observe the operation of password input, modification and so on.
5 Conclusion
This paper makes up for the shortcomings of the traditional password lock technology, and develops a logic circuit based on the VHDL language and EDA technology on the programmable chip CPLD. Since all passwords are stored and operated in pure hardware, the logic execution speed is much higher than that of the microcontroller. Make full use of the logic programmability of CPLD, short development cycle and high efficiency. The designed products have high reliability, low power consumption, small size and easy maintenance, which is bound to win in the security market.Wall Switch Sockets,Sockets And Switches,Light Switches And Sockets,Switch Socket Outlet
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