Artificial intelligence (AI) can be said to be the hottest topic in the computing field in 2016. The war of manufacturers competing to develop dedicated chips has already started...
Continued from the previous article: "What are the obstacles to the artificial intelligence chip warfare? 》
CEA's ambition is to develop neuromorphic circuits; the research organization believes that such chips are an effective complement to information from the proximity sensor's data (informaTIon) in deep learning applications.
Before achieving the above goals, CEA considered several expediencies; development tools such as D2N2 are important for chip designers to develop high-quality custom DNN solutions with per tera TOPS (tera operaTIons per second per Watt) performance. .
For those who want to use DNN in edge computing, there is also real hardware that can be tested—the ultra-low-power programmable accelerator P-Neuro from CEA; the current P-Neuro neural network processing unit is FPGA Based on this, Duranton said that CEA is about to turn the FPGA into an ASIC.
Duranton used the FPGA-based P-Neuro in the CEA lab to showcase the Convolutional Neural Network (CNN) for the face and P-Neuro with the embedded CPU (on the Raspberry Pi). The four-core ARM processor and the Android platform using the Samsung Exynos processor are all performing the same embedded CNN application, and the task is to perform "face feature extraction" in a database containing 18,000 images.
Performance comparison between P-Neuro and embedded CPU/GPU performing the same face recognition task
As shown in the above table, the speed of P-Neuro is 6,942 images per second, and the energy efficiency is 2,776 images per watt; compared with the embedded GPU (Tegra K1), P-Neuro operating at 1000MHz Faster and more energy efficient. P-Neuro is built on a clustered SIMD architecture that supports optimized memory tiering and internal linking.
P-Neuro function block
But for CEA researchers, P-Neuro is only a short-term solution; the current P-Neuro is built with full CMOS components and binary coded; the team is also building full CMOS components using spike coding. To take advantage of advanced process advantages and breakthroughs in density and power, the team set a higher goal.
For example, Carlo Reita, director of marketing and strategy for nanoelectronics technology at CEA-LeTI, said in an interview that the use of advanced chip and memory technology for the physical design of dedicated components is very important; one solution is CEA-LeTI's CoolCube conventional monolithic 3D Integration technology, another approach is to use resistive memory (Resistive RAM) as a synaptic component. In addition, advanced technologies such as FD-SOI and nanowires will also play a role.
Neuromorphic processorAt the same time, the EU under the "EU Horizon 2020" program, trying to build a neuromorphic architecture chip, can support the most advanced machine learning, and the spine-based learning mechanism; the research project is called NeuRAM3, the goal is to be ultra-low Power-consuming, scalable, and highly configurable neural architecture that creates components that consume 50 times less power than traditional digital solutions in specific applications.
Neuromorphic processor architecture 
Neuromorphic processor basic specifications
Reita said that CEA is also involved in the NeuRAM3 project, whose research goals are closely related to the mission of the project, including the development of monolithically integrated 3D technology using FD-SOI processes, and the integration of resistive memory synaptic components. Application; she also pointed out that the new generation of mixed-signal multi-core neuromorphic components developed by the NeuRAM3 project can significantly reduce power consumption compared to IBM's TrueNorth brain-inspired operands.
Comparison of NeuRAM3 neuromorphic components with IBM TrueNorth
Participants in the NeuRAM3 project include IMEC, IBM Zurich Research Center, ST Microelectronics, CNR (The National Research Council in Italy), Spanish research institute IMSE (El Instituto de Microelectronica de Sevilla in Spain), Switzerland The University of Zurich and Jacobs University in Germany.
Editor: Judith Cheng
(Reference: Race for AI Chips Begins, by Junko Yoshida)
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