Abstract : A PCI-I2S audio system method based on FPGA is proposed. By combining PCI soft core, FIFO and designed interface circuit in FPGA, a variety of buses such as PCI, I2C, I2S, etc. are implemented on FPGA, and the audio decoder is used to realize the transmission and playback of voice data with different sampling frequencies Features. The system makes full use of FPGA's on-chip resources and its programmable features, reducing the complexity of hardware circuits.
The I2S bus is a serial bus standard for transmitting data between audio devices. The bus uses independent clock lines and data lines to avoid time-induced distortion. With the widespread use of multimedia, this bus has been used in more and more digital systems.
The PCI bus is a high-performance 32 / 64-bit local bus. The theoretical maximum transmission rate can reach 132 Mbit · s-1, which can support multiple sets of peripherals. It has been marked as a bus by various mainstream processors and is currently used. The most extensive peripheral bus. Most processors today do not have an integrated I2S interface, but in embedded systems the CPU often uses the PCI bus to interact with peripheral devices, so a PCI-I2S interface conversion circuit needs to be designed to enable the CPU to communicate with peripheral audio devices. At present, such an interface conversion circuit is mainly implemented by combining a PCI interface chip and an audio interface chip and other special integrated circuit chips at a board-level circuit to implement a PCI-based audio playback device. Although this type of circuit is mature and reliable, the circuit design is complex, flexible, and requires a large amount of circuit board space.
With the development of digital communication technology, due to the flexibility of FPGA and its short development cycle, the application in interface circuit design has become more and more extensive. This paper proposes an interface conversion circuit that uses FPGA to implement PIC-I2S, which not only avoids the use of protocol conversion chips, saves space on the circuit board, but also greatly enhances the flexibility of the system and facilitates maintenance and upgrades.
1 System hardware designThe audio playback system is mainly composed of stereo audio codec TLN320AIC23B, FPGA device XC6SLX75 and processor PowerPC8270. The system block diagram is shown in Figure 1. The CPU transmits the original audio data to the FPGA through the PCI bus and transmits it to the audio chip TLV320AIC23B serially in the format of 16 bits of data for each group, and the audio chip converts the digital quantity into an analog audio signal output. The FPGA implements the PCI interface function and the configuration and data transmission function of the audio codec chip. The internal part is mainly composed of a PCI protocol interface, an I2S protocol interface, an I2S configuration register, an I2C protocol interface, and a FIFO memory.
TLV320AIC23B realizes the conversion of digital audio information to audio analog in the system. When the system is powered on, it needs to configure its multiple control registers through the I2C interface. After that, the chip will control the bit transmission clock (Bclk) and the left and right channels. The clock (LRCIN) collects audio data sent by the FPGA as configured in the control register. The received data will be transferred to the chip for digital-to-analog conversion and filtering.
According to the I2S protocol specification and chip requirements, FPGA divides the main clock (MCLK) to generate the bit transmission clock (Bclk) and the left and right channel control clock (LRCIN), and sends it to the TLV320AIC23B in synchronization with the audio data. The left and right channel control clock (LRCIN) should be the same frequency as the original sampling level of the audio data, according to I. S's protocol specification and chip information, its bit transmission clock (Bclk) and chip's master clock (MCLK) are as follows:
BCLK = Sampling Size & TImes; Sampling Rate (1)
MCLK = Sampling Size & TImes; Sampling Rate & TImes; 384 (2)
In the formula, Sampling Rate is the original sampling level frequency; SamplingSize is the sampling size.
In the system, the TLV320AIC23B chip uses a left-justified interface mode, and its timing is shown in Figure 2. Among them, the left channel of the audio is gated when LRCIN is high, and the right channel of the audio is low. In one cycle of LRCIN, the same set of data is transmitted on the left and right channels. Because the transmission speed of the PCI bus is much higher than the transmission speed of the I2S bus, in order not to interrupt the CPU's excessively high frequency response, a FIFO is generated in the FPGA so that the PCI bus can continuously transfer a large amount of data. In addition, because different audio files have different sampling level frequencies, and the sampling frequency of audio files is usually 16 kHz or 32 kHz, the I2S_config register is generated in the FPGA, which can be set through the PCI bus to call different numbers in the FPGA Clock management (DCM) to provide different clocks for the TLV320AIC23B chip.
The PCI protocol is more complex. It not only has strict synchronization timing requirements, but also requires many configuration registers, so the implementation circuit is also more complicated. Generally, there are three ways to implement PCI interface in FPGA: (1) Use PCI to design PCI interface by yourself. This method can selectively implement PCI interface function according to needs, which is closer to the needs of the system and can reduce system cost. However, developers need to have a deep understanding of the PCI protocol, and when the external environment is harsh, it is not easy to meet the stability requirements of the system, and it is difficult to develop. (2) Utilize PCI hard core to develop the system, PCI hard core is a solidified circuit embedded in FPCA, similar to the dedicated PCI interface chip, the designer only needs to complete the signal link and verification, but this method , PCI hard core has been solidified in FPGA, which affects the flexibility of the system. (3) Developed with PCI soft core, PCI soft core can be configured according to the user's own needs, which is more flexible and close to the user system, and it has been verified by the design manufacturer and has high reliability. This article uses the open source soft core MPCI32 provided by Mentor for the development of the PCI interface on the FPGA.
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